1. Field of the Invention
The present invention relates to, for example, an exposure apparatus that scans a mask by a charged particle beam to project a pattern, an exposure method, and a semiconductor device production method forming a circuit pattern of the semiconductor device by using the exposure method.
2. Description of the Related Art
A proximity exposure technology of equal scale that a mask called as a stencil mask that a mask pattern is formed by an aperture is located close to a wafer and a low acceleration electron beam is irradiated to the mask to perform an exposure is disclosed (refer to Japanese examined patent publication No. 2951947). For realizing this exposure technology, the development of a stencil mask with a thin film, which is called as membrane, having a thickness from about 500 nm to 1 μm and the development of resist process of 100 nm or less are performed now.
For keeping mechanical strength of the membrane that the aperture of the pattern is formed, it is necessary that size of one membrane is reduced and a mask structure that the membrane is sectioned small and reinforced by beams (strut) is suggested (refer to Japanese unexamined patent publication No. 2003-59819). In this case, since the aperture of the pattern cannot be formed at the position of the beam, a complementary division technology that desired circuit pattern is projected by dividing a circuit pattern that should be projected on the wafer, forming each divided pattern on a plurality of membranes, and overlapping the membranes to expose that is necessary.
In the above Japanese unexamined patent publication No. 2003-59819, size of one membrane is decided as about from 1 mm to 3 mm by sectioning by beams, then a mask that arrangement of the beams on four mask regions is displaced is disclosed. By overlapping four mask regions to expose them, a predetermined circuit pattern is projected on the wafer. In the mask described in the above Japanese unexamined patent publication No. 2003-59819, size of one mask region is about as large as size of a die (chip) that is a unit exposed region of the wafer.
Therefore, in the method described in the above Japanese unexamined patent publication No. 2003-59819, in the case that four mask regions formed on the stencil mask are scanned once, the scanning range of an electron beam is twice the die or more in both length and breadth. In the proximity exposure technology of equal scale disclosed in the Japanese examined patent publication No. 2951947, if the scanning range of the electron beam is large, it is difficult to keep electron beam parallel and to scan by the beam with a high accuracy.
As mentioned above, for improving mechanical strength of a mask, it is preferable that a membrane is sectioned small by a plurality of beams and size of one membrane is reduced about 1 mm to 3 mm. However, if the membrane is sectioned by a plurality of beams, since an aperture of the pattern cannot be formed at the position of the beams, for example like a mask structure described in the Japanese unexamined patent publication No. 2003-59819, there is a problem that four mask regions of the same size as the die is needed, and the scanning range of the electron beam becomes large. Moreover, if the membrane is sectioned small by the beams, the problem that complementary division of the pattern becomes complicated arises.
Meanwhile, in recent years, there is a prospect that it is realized that size of membrane is about 2.0 mm (July 2003, the fourth LEEPL forum). If a stencil mask having one membrane without the beams is realized, the scanning range of the electron beam may be larger than size of the die to a certain degree, and the above problem seems to be solved.
However, if size of one membrane forming an aperture of the pattern becomes large, an important issue such as rise in temperature because of the following reason in exposing and generation of displacement of the pattern position over an acceptable value associated with this occurred.
A reason of rise in temperature is that electron beams made to scan on the membrane overlap. Note that the above Japanese examined patent publication No. 2951947 describes that rise in temperature does not occurs only because energy of the used electron beam is small. However, since rise in temperature is really decided by a product of energy of the electron beam and time of irradiating the electron beam, even if using a low energy electron beam if time of irradiating is long, temperature of the membrane rises. Since time of irradiating the electron beam is decided by exposed resist sensitivity, it is necessary to discuss presence or absence of rise in temperature of the membrane in consideration of the resist sensitivity.
As described later, even in the case that energy of the electron beam is small as 2 keV like actual LEEPL, if the membrane size is made to be large, rise in temperature to the degree that displacement of the pattern over an acceptable value occurs is confirmed.
The other reason of rise in temperature is that decay time of temperature risen once of the membrane is proportional to the square of size of the membrane (refer to “Rate processes”, Hiroshi Komiyama work, Asakura bookstore, 1990). Therefore, if size of the membrane becomes too large, time required for temperature to restitute becomes longer. Consequently, the electron beams overlap and are irradiated on the membrane in a condition that temperature does not restitute, temperature of the membrane rises further, and displacement of position of the pattern formed on the membrane increases. Note that there is no description concerning decay of temperature in the above Japanese examined Patent Publication No. 2951947.
As mentioned above, in the case that size of the membrane is made to be large, an important issue such as rise in temperature of the membrane and displacement of the pattern position associated with that occurred. If the pattern position is displaced, error arises in the project pattern projected to the wafer arises and the pattern cannot be projected with a high accuracy.